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74VHC74 dual d-type flip flop with preset and clear september 1998 n high speed: f max =170 mhz (typ.) at v cc =5v n low power dissipation: i cc =2 m a (max.) at t a =25 o c n high noise immunity: v nih =v nil = 28% v cc (min.) n power down protection on inputs n symmetrical output impedance: |i oh |=i ol =8 ma(min) n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2v to 5.5v n pin and function compatible with 74 series 74 n improved latch-up immunity n low noise: v olp =0.8v(max.) description the 74VHC74 is an advanced high-speed cmos dual d-type flip flop with preset and clear fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. it has similar high speed performance of equivalent bipolar schottky ttl combined with true cmos low power dissipation. a signal on the d input is transfered to the q output during the positive going transition of the clock pulse. clear and preset are independent of the clock and accomplished by a low setting on the appropriate input. it is ideal for low power applications maintaining high speed operation similar to equivalent bipolar schottky ttl. power down protection is provided on all inputs and 0 to 7v can be accepted on inputs with no regard to the supply voltage. this device can be used to interface 5v to 3v. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess pin connection and iec logic symbols order codes : 74VHC74m 74VHC74t m (micro package) t (tssop package) ? 1/11
input equivalent circuit logic diagrams pin description pin no symbol name and function 1, 13 1clr, 2clr asyncronous reset - direct input 2, 12 1d, 2d data input 3, 11 1ck, 2ck clock input (low-to-high, edge- triggered) 4, 10 1pr, 2pr asyncronous set - direct input 5, 9 1q, 2q true flip-flop outputs 6, 8 1q, 2q complement flip-flop outputs 7 gnd ground (0v) 14 v cc positive supply voltage truth table inputs outputs function clrprdckq q l h x x l h clear h l x x h l preset llxxhh hhl lh hhh hl hhx q n q n no change x: don't care this logic diagram has not be used to estimate propagation delays 74VHC74 2/11
absolute maximum ratings symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current - 20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 50 ma t stg storage temperature -65 to +150 o c t l lead temperature (10 sec) 300 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these condition is not implied. recommended operating conditions symbol parameter value unit v cc supply voltage 2.0 to 5.5 v v i input voltage 0 to 5.5 v v o output voltage 0 to v cc v t op operating temperature -40 to +85 o c dt/dv input rise and fall time (see note 1) (v cc =3.3 0.3v) (v cc =5.0 0.5v) 0 to 100 0to20 ns/v ns/v 1) v in from 30% to 70% of v cc dc specifications symbol parameter test conditions value unit v cc (v) t a =25 o c-40to85 o c min. typ. max. min. max. v ih high level input voltage 2.0 1.5 1.5 v 3.0 to 5.5 0.7v cc 0.7v cc v il low level input voltage 2.0 0.5 0.5 v 3.0 to 5.5 0.3v cc 0.3v cc v oh high level output voltage 2.0 v i (*) = v ih or v il i o =-50 m a 1.9 2.0 1.9 v 3.0 i o =-50 m a 2.9 3.0 2.9 4.5 i o =-50 m a 4.4 4.5 4.4 3.0 i o =-4 ma 2.58 2.48 4.5 i o =-8 ma 3.94 3.8 v ol low level output voltage 2.0 v i (*) = v ih or v il i o =50 m a 0.0 0.1 0.1 v 3.0 i o =50 m a 0.0 0.1 0.1 4.5 i o =50 m a 0.0 0.1 0.1 3.0 i o =4 ma 0.36 0.44 4.5 i o =8 ma 0.36 0.44 i i input leakage current 0 to 5.5 v i = 5.5v or gnd 0.1 1.0 m a i cc quiescent supply current 5.5 v i =v cc or gnd 2 20 m a (*) all outputs loaded. 74VHC74 3/11
ac electrical characteristics (input t r =t f =3 ns) symbol parameter test condition value unit v cc (v) c l (pf) t a =25 o c-40to85 o c min. typ. max. min. max. t plh t phl propagation delay time ck to q or q 3.3 (*) 15 6.7 11.9 1.0 14.0 ns 3.3 (*) 50 9.2 15.4 1.0 17.5 5.0 (**) 15 4.6 7.3 1.0 8.5 5.0 (**) 50 6.1 9.3 1.0 10.5 t plh t phl propagation delay time pr or clr to q or q 3.3 (*) 15 7.6 12.3 1.0 14.5 ns 3.3 (*) 50 10.1 15.8 1.0 18.0 5.0 (**) 15 4.8 7.7 1.0 9.0 5.0 (**) 50 6.3 9.7 1.0 11.0 t w ck pulse width high or low 3.3 (*) 6.0 7.0 ns 5.0 (**) 5.0 5.0 t w pr or clr pulse width low 3.3 (*) 6.0 7.0 ns 5.0 (**) 5.0 5.0 t s setup time d to ck high or low 3.3 (*) 6.0 7.0 ns 5.0 (**) 5.0 5.0 t h hold time d to ck high or low 3.3 (*) 0.5 0.5 ns 5.0 (**) 0.5 0.5 t rem removal time clr or pr to ck 3.3 (*) 5.0 5.0 ns 5.0 (**) 3.0 3.0 f max maximum clock frequency 3.3 (*) 15 80 125 70 mhz 3.3 (*) 50 50 75 45 5.0 (**) 15 130 170 110 5.0 (**) 50 90 115 75 (*) voltage range is 3.3v 0.3v (**) voltage range is 5v 0.5v capacitive characteristics symbol parameter test conditions value unit v cc (v) t a =25 o c-40to85 o c min. typ. max. min. max. c in input capacitance 3.3 410 10 pf c pd power dissipation capacitance (note 1) 3.3 f in = 10 mhz 25 pf 1) c pd is defined as the value of the ic's internal equivalent capacitance which is calculated from the operating current consumption without load. (refer t o test circuit). average operting current can be obtained by the following equation. i cc (opr) = c pd ? v cc ? f in +i cc /2 (per flip-fliop) 74VHC74 4/11
dynamic switching characteristics symbol parameter test conditions value unit v cc (v) t a =25 o c-40to85 o c min. typ. max. min. max. v olp dynamic low voltage quiet output (note 1, 2) 5.0 c l =50pf 0.3 0.8 v v olv -0.8 -0.3 v ihd dynamic high voltage input (note 1, 3) 5.0 3.5 v ild dynamic low voltage input (note 1, 3) 5.0 1.5 1) worst case package. 2) max number of outputs defined as (n). data inputs are driven 0v to 5.0v, (n -1) outputs switching and one output at gnd. 3) max number of data inputs (n) switching. (n-1) switching 0v to 5.0v. inputs under test switching: 5.0v to threshold (v ild ), 0v to threshold (v ihd ), f=1mhz. test circuit c l = 15/50 pf or equivalent (includes jig and probe capacitance) r t =z out of pulse generator (typically 50 w ) 74VHC74 5/11
waveform 1: propagation delays, setup and hold times (f=1mhz; 50% duty cycle) 74VHC74 6/11
waveform 2: propagation delays (f=1mhz; 50% duty cycle) 74VHC74 7/11
waveform 3: recovery times (f=1mhz; 50% duty cycle) waveform 3: pulse width 74VHC74 8/11
dim. mm inch min. typ. max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 8.55 8.75 0.336 0.344 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.68 0.026 s 8 (max.) p013g so-14 mechanical data 74VHC74 9/11
dim. mm inch min. typ. max. min. typ. max. a 1.1 0.433 a1 0.05 0.10 0.15 0.002 0.004 0.006 a2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 d 4.9 5 5.1 0.193 0.197 0.201 e 6.25 6.4 6.5 0.246 0.252 0.256 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 o 4 o 8 o 0 o 4 o 8 o l 0.50 0.60 0.70 0.020 0.024 0.028 c e b a2 a e1 d 1 pin 1 identification a1 l k e tssop14 mechanical data 74VHC74 10/11
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 1998 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. . 74VHC74 11/11

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